HW Design Verification Engineer (Junior / Senior)

Job Description Roles & Responsibilities About us: ASAL Technologies was established in the year 2000 and has since grown to become the foremost Technology Company across Jordan, UAE, and Palestine. With a workforce of over 450 engineers, ASAL offers an extensive variety of services in the field of software development and collaborates with more than 40 international clients. ASAL Technologies is the destination for high-quality, innovative, and cost-effective software development, data engineering, and R&D services. The name ASAL is derived from the Arabic word for Honey symbolizing the dedication of our engineers, who operate as hard-working bees, they consistently deliver exceptional results for our clients and become a technical arm to their R&D teams. About the Role: We are looking for passionate, talented, and detail-oriented Hardware Design Verification Engineers to join our growing hardware team. In this role, you will be responsible for verifying complex digital designs, ensuring the delivery of robust, reliable, and high-quality silicon through advanced verification methodologies. You will collaborate closely with architects, design engineers, software teams, and CAD specialists to develop and execute comprehensive verification plans, testbenches, and test suites for our advanced hardware products. This position is open to both entry-level (junior) and experienced (senior) candidates. The scope of responsibility will vary depending on experience. Key Responsibilities For All Levels Develop and execute verification plans based on design specifications. Build and maintain testbenches using Verilog, Specman, eRM, SystemVerilog, and UVM. Create and run simulation test cases to verify functionality and performance. Identify, debug, and track design and verification issues. Collaborate closely with design, architecture, and firmware teams. Analyze simulation results, coverage reports, and debug failures. Ensure high functional and code coverage. Additional Responsibilities Senior Level Define verification strategy and architecture for complex IPs or subsystems. Lead verification efforts and mentor junior engineers. Drive coverage closure and verification sign-off. Improve and optimize verification flows and methodologies. Contribute to automation, regression infrastructure, and CI flows. Participate in design reviews and provide feedback for verification readiness. For Junior Candidates Fresh graduates/undergraduates who will graduate this semester are welcome to apply as well. B.Sc./M.Sc. in Electrical Engineering, Computer Engineering, or related field. Basic understanding of digital design fundamentals (RTL, FSMs, pipelines). Familiarity with Verilog/SystemVerilog. Knowledge of object-oriented programming (OOP) and scripting languages such as Python, Perl, or Shell. Solid understanding of data structures and algorithms Strong analytical and problem-solving skills. Willingness to learn and grow in verification methodologies. Good communication and teamwork skills Ability to work independently and think critically to solve complex problems For Experienced Candidates 3+ years of experience in Design Verification. Strong hands-on experience with Specman, SystemVerilog and UVM. Proven experience in testbench development and debugging. Solid understanding of verification methodologies and coverage techniques. Experience with protocol-based verification (e.g., AMBA AXI, PCIe) advantage. Familiarity with tools such as VCS, Xcelium, or similar simulators. Experience in scripting languages (e.g., Python, Perl, or Tcl) advantage. Exposure to Continuous Integration (CI) workflow and version control systems (e.g., Git). What We Offer Opportunity to work on cutting-edge hardware technologies. Collaborative and innovative work environment. Professional growth and learning opportunities. Desired Candidate Profile For Junior Candidates Fresh graduates/undergraduates who will graduate this semester are welcome to apply as well. B.Sc./M.Sc. in Electrical Engineering, Computer Engineering, or related field. Basic understanding of digital design fundamentals (RTL, FSMs, pipelines). Familiarity with Verilog/SystemVerilog. Knowledge of object-oriented programming (OOP) and scripting languages such as Python, Perl, or Shell. Solid understanding of data structures and algorithms Strong analytical and problem-solving skills. Willingness to learn and grow in verification methodologies. Good communication and teamwork skills Ability to work independently and think critically to solve complex problems For Experienced Candidates 3+ years of experience in Design Verification. Strong hands-on experience with Specman, SystemVerilog and UVM. Proven experience in testbench development and debugging. Solid understanding of verification methodologies and coverage techniques. Experience with protocol-based verification (e.g., AMBA AXI, PCIe) advantage. Familiarity with tools such as VCS, Xcelium, or similar simulators. Experience in scripting languages (e.g., Python, Perl, or Tcl) advantage. Exposure to Continuous Integration (CI) workflow and version control systems (e.g., Git). Company Industry IT - Software Services Department / Functional Area Engineering Keywords HW Design Verification Engineer (Junior / Senior) Get real-time job updates only on our App