Digital Verification Manager / Sr Manager

Job Description Roles & Responsibilities Technical Leadership Role: Define and own the end-to-end verification strategy, including planning, coverage closure, and sign-off criteria. Architect and own the development of reusable UVM-based environments for different digital and mixed signal IPs verification Drive adoption and continuous improvement of verification methodologies (UVM, formal verification, etc.) Oversee AMS co-simulation strategies using real-number modeling and behavioral analog models Ensure comprehensive verification of different modes of operation including protocol corner cases, training sequences, error injection and recovery, loopback and test modes Implement assertion-based verification for calibration and training correctness Stay current with industry trends and emerging verification tools and technologies, driving their adoption where applicable Program Execution: Collaborate closely with RTL design, architecture, and mixed signal design teams to ensure seamless integration and verification of IP blocks Own verification schedules, resource planning, and risk mitigation across concurrent projects Engage with customers and partners on IP deliverables, verification collateral, and integration support Represent the verification team in program reviews, milestone sign-offs, and customer-facing discussions Establish and track KPIs and quality metrics for verification completeness and team productivity People and Team Management: Lead, mentor and grow the verification team Drive hiring, onboarding, performance reviews, and career development plans Foster a culture of technical excellence, peer review, knowledge sharing, and continuous improvement Drive team motivation through clear vision-setting, timely recognition of achievements, and visible support during critical project phases Allocate resources across multiple concurrent IP projects, balancing schedules, skill sets, and priorities Desired Candidate Profile Essential Qualifications and Experience: Bachelor's or Master's degree in Electrical Engineering or Computer Engineering 12+ Years of experience in VLSI Digital Design/Verification, with 3-5+ years in a people management or technical lead role Proven track record of taking IPs from spec to silicon-proven delivery Strong command of UVM and System Verilog; constrained-random verification, coverage-driven verification, and assertion-based verification Experience with gate-level simulation, X-propagation, and SDF back-annotation flows Solid understanding of mixed signal verification including real number modeling, behavioral modeling and AMS co-sim Experience verifying analog-digital interface boundaries, and calibration logic Strong understanding of Verilog RTL design techniques and tradeoffs Solid understanding of ASIC/FPGA design flows including RTL Synthesis, place and route, and timing sign-off Strong knowledge of Python/Perl/TCL/Shell scripting languages Experience working with global teams Desirable Qualifications and Experience: Knowledge of clock and reset domain crossing techniques Familiarity with ISO 26262 or other functional safety standards Experience using version control tools, and bug tracking software Familiarity with SERDES PHYs and Protocols Company Industry IT - Software Services Department / Functional Area Engineering Keywords Digital Verification Manager / Sr Manager Get real-time job updates only on our App