AI EDA Verification Engineer

Job Description Roles & Responsibilities At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. We are seeking an experienced AI EDA Specialist (Verification / Workflow SME) to bridge the gap between semiconductor verification methodologies and AI-driven automation. This role will serve as the domain expert responsible for validating AI-generated verification artifacts, debugging customer verification challenges, developing ground-truth datasets, and ensuring AI solutions align with industry-standard verification workflows. The ideal candidate combines deep expertise in SystemVerilog, UVM, simulation, and formal verification with a passion for enabling next-generation AI-powered engineering solutions Responsibilities Verification Workflow Validation Validate AI-generated outputs across RTL verification workflows. Review and assessment generated: UVM testbenches Assertions (SVA) Coverage strategies Simulation and formal verification flows Ensure compliance with industry-standard verification methodologies and best practices. Customer Technical Support & Debugging Investigate and resolve customer-reported issues involving: UVM environments RTL verification testbenches Functional coverage Assertion failures Simulation regressions Reproduce, analyze, and document root causes of complex verification problems. Partner closely with customers, application engineers, and product teams to drive issue resolution. Ground Truth & Benchmark Development Develop and maintain benchmark verification datasets and golden reference test cases. Establish correctness criteria for evaluating AI-generated verification artifacts. Build validation suites for model qualification and regression testing. AI Model Enablement Collaborate with AI/LLM engineers to improve accuracy and verification relevance of AI-generated outputs. Review model responses and provide feedback for fine-tuning and evaluation. Translate semiconductor verification workflows into structured AI evaluation scenarios. Help reduce hallucinations and improve technical correctness of AI-assisted verification solutions. EDA Workflow Integration Validate interoperability between AI systems and industry-standard EDA tools. Support workflow automation across: Simulation Regression management Coverage analysis Formal verification Identify opportunities to improve verification productivity through AI-assisted automation. Education Bachelor's or Master's degree in: Electrical Engineering Computer Engineering Computer Science Related technical discipline Experience 6 10 years of experience in semiconductor verification. Proven experience developing and debugging complex UVM-based verification environments. Hands-on experience with RTL, IP, subsystem, or SoC verification projects. Experience supporting customers or field engineering organizations. Familiarity with AI, LLMs, or AI-assisted EDA workflows. Experience developing verification automation frameworks. Knowledge of agentic AI systems and evaluation methodologies. Exposure to semiconductor EDA product development or application engineering. Technical Skills Verification Expertise Strong knowledge of: SystemVerilog UVM RTL Verification Functional Coverage Code Coverage Assertion-Based Verification (SVA) Constrained Random Methodologies Debug & Analysis Expertise debugging: Simulation failures Assertion violations Coverage gaps Verification regressions Complex multi-component testbenches EDA Tools Experience with one or more of the following: Cadence Xcelium Synopsys VCS Siemens QuestaSim Cadence JasperGold Synopsys VC Formal Verification management and regression platforms Automation Skills Python Shell scripting TCL scripting Workflow automation and test framework development Desired Candidate Profile Bachelor's or Master's degree in: Electrical Engineering Computer Engineering Computer Science Related technical discipline 6 10 years of experience in semiconductor verification. Proven experience developing and debugging complex UVM-based verification environments. Hands-on experience with RTL, IP, subsystem, or SoC verification projects. Experience supporting customers or field engineering organizations. Familiarity with AI, LLMs, or AI-assisted EDA workflows. Experience developing verification automation frameworks. Knowledge of agentic AI systems and evaluation methodologies. Exposure to semiconductor EDA product development or application engineering. Strong knowledge of: SystemVerilog UVM RTL Verification Functional Coverage Code Coverage Assertion-Based Verification (SVA) Constrained Random Methodologies Debugging expertise in: Simulation failures Assertion violations Coverage gaps Verification regressions Complex multi-component testbenches Experience with one or more of the following EDA tools: Cadence Xcelium Synopsys VCS Siemens QuestaSim Cadence JasperGold Synopsys VC Formal Verification management and regression platforms Automation skills in Python, Shell scripting, or TCL scripting, and workflow automation and test framework development. Company Industry IT - Software Services Department / Functional Area Engineering Keywords AI EDA Verification Engineer Get real-time job updates only on our App